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Dr. Ravneet Kaur

Dr. Ravneet Kaur (Assistant Professor) specializes in analytical analysis, characterization and simulation of short channel effects in sub-100nm MOSFET for high performance. Her research areas focused on the development of efficient 2D algorithms and optimization techniques for advanced sub-100nm MOS structures. Consideration has also been given to exploration of new architectures of Silicon on Insulator and Silicon On Nothing MOSFETs for enhanced performance and their applications in various different fields. She has also worked on modeling and simulations of HEMTs for high performance microwave circuits. She has authored or co-authored more than 66 papers in various international and national journals and conference proceedings. Dr. Kaur has been a reviewer for IEEE TRANSACTIONS ON ELECTRON DEVICES, Journal of Electrical and Electronics Engineering Research (JEEER) and for International Conference - Asia Pacific Microwave Conference (APMC)-2008 held from 16-19, December 2008 in Hong Kong Convention and Exhibition Center, China. Her name has been listed in 2010 edition of Who’s Who in the World. Her name appeared in the GOLDEN REPORT SELECTION.teS T-ED, IEEE TRANSACTIONS ON ELECTRON DEVICES, December 2008.

Title    Dr. First Name Ravneet Last Name Kaur Photograph
Designation Assistant Professor  
Department Electronics

Address
(Campus)

 

 

 

(Residence)

Acharya Narendra Dev College
Govind Puri,
Kalkaji
New Delhi-110019.
C1/102 GOLD CROFT, Plot No. 4, Sector 11, Dwarka, New Delhi- 110075
Phone Number
(Campus)
+ 9111 26412547, +91 11 26293224, +91 11 26294542
Mobile 09810836367

Email

ravneetsawhney13@rediffmail.com
Education Subject Institution
B. Sc. (H) Electronics ARSD College, University of Delhi, Dhaula Kuan
M. Sc. Electronics Department of Electronic Science, University of Delhi South Campus
Ph.D Electronic Science Department of Electronic Science, University of Delhi South Campus
Research Interests/ Specialization
Modeling and simulation of sub-100 nm MOSFET structures:
  1. Insulated Shallow Extension (ISE)
  2. Grooved/ Concave Gate
  3. Silicon on Insulator (SOI)
  4. Silicon on Nothing (SON)
  5. High Electron Mobility Transistor (HEMT)

Specialization: Microelectronics

Teaching Experience
  1. Undergraduate

                       B.Tech Electronics : Part-I
                            Foundation Course –Information Technology (FC3IT) 

                       B.Sc.(H) Electronics : Part-II
                             Instrumentation (Paper 2.4)
                             Numerical Analysis (Paper 2.7)
                             Numerical Techniques (Paper ELHT 401)
                             Electronics Practical-II (Paper 2.9)
                             Electronics Practical-V (ELHP 305)
                             Electronics Practical-VI (ELHP 306)
                             Electronics Practical-VII (ELHP 405)
                             Electronics Practical-VIII (ELHP 406)

                       B.Sc.(H) Electronics : Part-III

                            Communications (Paper 3.3)
                            Material Science and Integrated Circuit (Paper 3.5)
                            Electrical Technology and Electrical Machines (Paper 3.6)
                            Engineering Drawing (Paper 3.2)
                            Electronics Practical-III (Paper 3.8)
                            Electronics Practical-X (ELHP 506)

                        B.Sc.(H) Electronics : Part-I
                              Engineering Materials (ELHT 102)
                               Electronics Practical-I (Paper 1.9)

                                B.Sc.(H) Computer Science : Part-I
                                       Hardware lab based on Digital Electronics (CS 207)
                                        Digital Electronics (paper 104)
                                        Digital Electronics (ELHT 301)
                                        Lab based on Digital Electronics

             B. Sc.(Program) Foundation Course
                    IN-108 - Laboratory: Electronics and Modern Instrumentation
                    Electronics Laboratory-I (Paper PS 102.2)

             B. Sc. Physical Sciences(Concurrent Course): Part-III
                    Communication Electronics (ELCT-602)
                    Communication Practical (ELCP-606)

Post-graduate:
         M.Sc Electronics (1st Semester)
              High Level Computer Language -C++ (Paper 1.1)
              High Level Computer Language and Operating System lab (paper 1.5)

 

Scholarships/Awards
  • Name listed in 2009 edition of Who Who in the World
  • Name appeared in the Golden Report Selections T-ED, IEEE Transactions on Electron Devices, vol. 55, no. 12, December 2008.
  • Received All India Post Graduate Scholarships for the tenure of Post graduation, M.Sc (Electronics).
  • Awarded full fellowship in Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007) Mumbai, December 16-20, 2007.
  • Gold medallist in M.Sc.Electronics, University of Delhi South Campus and received Smt. Shanti Devi Bhargava Memorial Gold medal for being the best candidate in the M. Sc. Examination in Electronics in 2004.
  • Junior Research Fellowship (DRDO sponsored project): April 1, 2005 - April 30 ,2007
  • Senior Research Fellowship (DRDO sponsored project): May 1, 2007- November 20,2007
  • Received the Delhi Sanskrit Academy Award in Secondary Board Examination, 1997
Research/ Academic Projects
Research Projects
  • DRDO sponsored project entitled, “Two Dimensional Physics Based Modeling and Simulation of a Graded Channel (GC) Multiple Gate SOI- MOSFET for sub 100nm Device Dimension for High Performance Analog Applications"

Academics Projects     

  • 8085 Microprocessor based Traffic Light Controller with a Digital Counter.
  • Validation and study of Data communication in optical medium using Optical multiplexing unit OMUX-32.
  • Design and simulation of Integrated Optical Devices using BPM CAD.

Publications (Last Five Years)
In Indexed/Peer Reviewed Journals
Year of Publication Title Journal Co-author/s
2007 Performance Investigation of 50nm Insulated Shallow Extension Gate Stack (ISEGaS) MOSFET for Mixed Mode Applications IEEE Transactions on Electron Devices Rishu Chaujar, Manoj Saxena and R. S. Gupta
2007 Unified Subthreshold Model for Channel Engineered Sub-100nm Advanced MOSFET Structures IEEE Transactions on Electron Devices Rishu Chaujar, Manoj Saxena and R. S. Gupta
2007 Hot carrier reliability and analog performance investigation of DMG-ISEGaS MOSFET IEEE Transactions on Electron Devices Rishu Chaujar, Manoj Saxena and R. S. Gupta
2007 Two-Dimensional Analytical Model to Characterize Novel MOSFET Architecture: Insulated Shallow Extension (ISE) MOSFET Semiconductor Science and Technology Rishu Chaujar, Manoj Saxena and R. S. Gupta
2007 Lateral Channel Engineered - Hetero Material Insulated Shallow Extension Gate Stack (HMISEGAS) MOSFET Structure: High Performance RF Solution for MOS Technology Semiconductor Science and Technology Rishu Chaujar, Manoj Saxena and R. S. Gupta
2008 Laterally amalgamated DUal amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET For ULSI Micro Electronic Engineering Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta
2008 Two-Dimensional Analytical Sub-Threshold Model of Multi-Layered Gate Dielectric Recessed Channel (MLaG-RC) Nanoscale MOSFET Semiconductor Science and Technology Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta
2008 Intermodulation Distortion and Linearity Performance Assessment of 50-nm gate length L-DUMGAC MOSFET for RFIC Design Superlattices and Microstructures Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta
2008 Investigation of Multi-Layered-Gate Electrode Workfunction Engineered Recessed Channel (MLGEWE-RC) Sub-50nm MOSFET: A Novel Design International Journal of Numerical Modeling: Electronic Networks, Devices and Fields Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta
2008 TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its Multi-Layered Gate Architecture: Part-I: Hot Carrier Reliability Evaluation IEEE Transactions on Electron Devices Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta
2008 On-State and RF Performance Investigation of Sub-50nm L-DUMGAC MOSFET Design for High-Speed Logic and Switching Applications Semiconductor Science and Technology Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta
2008 Modeling and Analysis of fully strained and partially relaxed lattice mismatched AlGaN/GaN HEMT for High Temperature Applications Superlattices and Microstructures Parvesh Gangwani, Sujata Pandey, Subhasis Haldar, Mridula Gupta and R.S. Gupta
2009 Two-Dimensional Analytical Modeling of a Novel Gate-Stack ISE MOSFET. Micro Electronic Engineering Rishu Chaujar, Manoj Saxena and R. S. Gupta
2009 Two-dimensional threshold voltage model and design considerations for gate electrode work function engineered recessed channel nanoscale MOSFET: I. Semiconductor Science and Technology Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta
2009 T-gate Geometric (Solution for Submicrometer Gate Length) HEMT: Physical Analysis, Modeling and Implementation as Parasitic Elements and its usage as Dual Gate for Variable Gain Amplifiers. Superlattices and Microstructures Ritesh Gupta, Servin Rathi,  Mridula Gupta and Radhey S Gupta
2009 “TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its multi-layered gate architecture, Part II: Analog and large signal performance evaluation Superlattices and Microstructures Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta
2010 Hot Carrier Reliability Monitoring of DMG ISE SON MOSFET for Improved Analog Performance Microwave and Optical Technology Letters Rishu Chaujar, Manoj Saxena and R. S. Gupta,
2010 Design Considerations and Impact of Technological Parametric Variations on Rf/Microwave Performance of GEWE-RC MOSFET Microwave and Optical Technology Letters Rishu Chaujar, Manoj Saxena, Mridula Gupta and R.S. Gupta
Conference  Publications
Year of Publication Title Journal Co-author/s
2005 Investigating the role of Stacked Gate Oxide and Hetro-Material Gate on Electrical Characteristics of Insulated Shallow Extension (ISE) MOSFET Thirteenth International Workshop  on Physics of Semiconductor Devices (IWPSD-2005) 13-17 December 2005,New Delhi India. Manoj Saxena and R. S. Gupta
2006 RF Performance Investigation of Gate Stacked Insulated Shallow Extension (ISE) MOSFET and Bulk: A Comparative Study National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2006), 24-26 March 2006, New Delhi, India. Rishu Chaujar, Manoj Saxena and R. S. Gupta
2006 Design and FPGA realization of Direct Sequence-Spread Spectrum (DS-SS) BPSK Modulator using a Five Stage Gold Code Generator National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2006), 24-26 March 2006, New Delhi, India.
 
Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta,  
2006 Scrambled Sequence FPGA based Direct Sequence Spread Spectrum BPSK Modulator: 10 Stage Analysis National Conference on Recent Trends in Electronics and Information Technology, (RTEIT 2006), 28-29 July 2006, Kopargaon Maharashtra, India. Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta, 
2006 Lateral Channel Engineered Structure- Insulated Shallow Extension (ISE) MOSFET: DC and RF Performance Investigation National Conference on Recent Advancement in Microwave Technique and Applications (Microwave-2006), 6-8 October 2006, Jaipur, India.
2006 Exploring the Effect of Negative Junction Depth on Electrical Behaviour of Sub-50-Nanometer Concave DMG MOSFET: A Simulation Study National Conference on Recent Advancement in Microwave Technique and Applications (Microwave-2006), 6-8 October 2006, Jaipur, India. Rishu Chaujar, Manoj Saxena and R. S. Gupta
2006 Gate Oxide Engineered Dual Material Gate Insulated Shallow Extension (GOXDMG-ISE) MOSFET: A New Vent to Wireless Communication 3rd International Conference on Computers and Devices for Communication (CODEC-2006), Institute of Radio physics and Electronics, university of Calcutta, December 18-20, 2006. Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta  
2006 Exploration of the Effect of Negative Junction Depth on the Electrical Characteristics of Concave DMG MOSFET in Sub-50-Nanometer 3rd International Conference on Computers and Devices for Communication (CODEC-2006), Institute of Radio physics and Electronics, university of Calcutta, December 18-20, 2006. Rishu Chaujar, Manoj Saxena and R. S. Gupta
2007 Effect of transport property on the performance of insulated shallow extension gate stack (ISEGaS) MOSFET Indian microelectronics Society Conference 2007 Theme: Trends in VLSI and Embedded System, August 17-18, 2007, Panjab  
2007 New Concave MOSFET with Transverse Dual Material Gate (T-DMG) in Sub-50nm Regime: A Simulation Study
Engineering College, Chandigarh, India.
Indian microelectronics Society Conference 2007 Theme: Trends in VLSI and Embedded System, August 17-18, 2007, Panjab Engineering College, Chandigarh, India. Rishu Chaujar, Manoj Saxena and R. S. Gupta
2007 Nanoscale Insulated Shallow Extension MOSFET with Dual Material Gate for High Performance Analog Operations Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007) Mumbai, December 16-20, 2007. Rishu Chaujar, Manoj Saxena and R. S. Gupta
2007 Subthreshold Performance Consideration of a Novel Architecture: ISEGaS deca-nanometer MOSFET

Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007) Mumbai, December 16-20, 2007.

Rishu Chaujar, Manoj Saxena and R. S. Gupta
2007 RF-Distortion in Sub-100nm L-DUMGAC MOSFET

Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007) Mumbai, December 16-20, 2007.

Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta
2007 Two-Dimensional Analytical Threshold Voltage Model for Nanoscale SG-Concave MOSFET in Sub-50nm Regime Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007) Mumbai, December 16-20, 2007. Rishu Chaujar, Manoj Saxena and R. S. Gupta
2007 Linearity Assessment in DMG ISEGaS MOSFET for RFIC Design Nineteenth Asia Pacific Microwave Conference, APMC 2007, December 11-14, 2007, Bangkok, Thailand. Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta
2007 Electrical Characterization of Insulated Shallow Extension (ISE) MOSFET: A Punchthrough Stopper 11th International Symposium on. Microwave and Optical Technology (ISMOT 2007) Villa Mondragone, Monte Porzio Catone, Italy, 17-21 December 2007. Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta
2007 Pre-Distortion Linearity Enhancement for Sub-50nm Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET 11th International Symposium on. Microwave and Optical Technology (ISMOT 2007) Villa Mondragone, Monte Porzio Catone, Italy, 17-21 December 2007. Rishu Chaujar, Manoj Saxena and R. S. Gupta
2007 Two-Dimensional Simulation of C-V Characteristics of Deep Submicron AlmGa1-mN/GaN HEMT for Microwave Applications 11th International Symposium on. Microwave and Optical Technology (ISMOT 2007) Villa Mondragone, Monte Porzio Catone, Italy, 17-21 December 2007. Rishu Chaujar, Manoj Saxena and R. S. Gupta
2007 On-State and Switching Performance Investigation of Sub-50nm L-DUMGAC MOSFET Design for High-Speed Logic Applications International Semiconductor Device Research Symposium (ISDRS 2007) University of Maryland, USA, December 12-14, 2007. Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta
2007 2-Dimensional Simulation and Characterization of Deep Submicron AlGaN/GaN HEMTs for High Frequency Applications  International Semiconductor Device Research Symposium (ISDRS 2007) University of Maryland, USA,, December 12-14, 2007. Parvesh Gangwani, Sujata Pandey , Subhasis Haldar, Mridula Gupta and R. S. Gupta
2007 Dual Material Gate (DMG) SOI-MOSFET with Dielectric Pockets: Innovative Sub-50 nm design for improved switching performance Indo-Australian Symposium on Multifunctional Nanomaterials, Nanostructures and Applications (MNNA 2007), December 19–21, 2007, New Delhi, India. Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta
2007 Two-Dimensional Analytical Modeling and Simulation of Rectangular Gate Recessed Channel (RG-RC) Nanoscale MOSFET in Sub-50nm Regime Indo-Australian Symposium on Multifunctional Nanomaterials, Nanostructures and Applications (MNNA 2007), December 19–21,
2007, New Delhi, India.
Parvesh, Sujata Pandey, Subhasis Haldar, Mridula Gupta and R. S. Gupta
2008 Nanoscale Analytical Modeling and TCAD Simulations of a Novel Gate Dielectric Stack SDPI MOSFET 2nd IEEE International Nanoelectronics Conference (INEC-2008), March 24-27, 2008, Shanghai, China. Rishu Chaujar, Manoj Saxena and R. S. Gupta
2008 TCAD Investigation of Hot Carrier Reliability Issues Associated with GEWE-RC MOSFET 2nd IEEE International Nanoelectronics Conference (INEC-2008), March 24-27, 2008, Shanghai, China. Rishu Chaujar, Manoj Saxena and R. S. Gupta
2008 Sub-Threshold Drain Current Performance Assessment of MLGEWE-RC MOSFET for CMOS Technology IEEE Sponsored Mini Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed Mode Applications-2008, January 5-6 2008, South Campus, Delhi University, New Delhi, India. Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta
2008 RF Performance Assessment of L-DUMGAC MOSFET for Future CMOS Technology in GigaHertz Regime IEEE Sponsored Mini Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed Mode Applications-2008, January 5-6 2008, South Campus, Delhi University, New Delhi, India Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta
2008 TCAD Investigation of a Novel MOSFET Architecture of DMG ISE SON MOSFET for ULSI Era IEEE Sponsored Mini Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed Mode Applications-2008, January 5-6 2008, South Campus, Delhi University, New Delhi, India. Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta
2008 Analytical Analysis of Sub-Threshold Performance of Sub-100nm Advanced MOSFET Structures-An Iterative Approach IEEE Sponsored Mini Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed Mode Applications-2008, January 5-6 2008, South Campus, Delhi University, New Delhi, India. Rishu Chaujar, Manoj Saxena and R. S. Gupta
2008 Modeling of nitride based Hetrojunction Transistors for RF Applications Mini Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed Mode Applications-2008, January 5-6 2008, South Campus, Delhi University, New Delhi, India. Rishu Chaujar, Manoj Saxena and R. S. Gupta
2008 Temperature Dependent Analytical Model of AlGaN/GaN HEMT Mini Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed Mode Applications-2008, January 5-6 2008, South Campus, Delhi University, New Delhi, India. Parvesh, Sujata Pandey, Subhasis Haldar, Mridula Gupta and R. S. Gupta
2008 Pre-Distortion Assessment of Workfunction Engineered Multi-Layer Dielectric Design of DMG ISE SON MOSFET 11th International Conference on Modeling and Simulation of Microsystems (MSM-2008),  June 1-5, 2008, Boston, Massachusetts, U.S.A. Parvesh, Sujata Pandey, Subhasis Haldar, Mridula Gupta and R. S. Gupta
2008 An Iterative Approach to Characterize Various Advanced Non-Uniformly Doped Channel Profiles 2008 Workshop on Compact Modeling (WCM-2008), June 1-5, 2008, Boston, Massachusetts, U.S.A. R. Chaujar, M. Saxena and R. S. Gupta
2008 Compact Analytical Threshold Voltage Model for Nanoscale Multi-Layered-Gate Electrode Workfunction Engineered Recessed Channel (MLGEWE-RC) MOSFET 2008 Workshop on Compact Modeling (WCM-2008), June 1-5, 2008, Boston, Massachusetts, U.S.A. R. Chaujar, M. Saxena and R. S. Gupta
2008 Assessment of L-DUMGAC MOSFET for High Performance RF Applications with Intrinsic Delay and Stability as Design Tools 11th International Conference on Modeling and Simulation of Microsystems (MSM-2008),  June 1-5, 2008, Boston, Massachusetts, U.S.A. R. Chaujar, M. Saxena, M. Gupta and R. S. Gupta
2008 Impact of Multi-Layered Gate Design on Hot Carrier Reliability of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET XXIX General Assembly of the International Union of Radio Science (Union Radio Scientifique Internationale-URSI), Illinois, USA, August 07-16, 2008. R. Chaujar, M. Saxena, M. Gupta and R. S. Gupta
2008 GEWE-RC MOSFET: A Solution to CMOS Technology for RFIC Design Based on the concept of Intercept Point International Conference on Recent Advancements in Microwave Theory and Applications (Microwave-2008), Jaipur, India, November 21-24, 2008 R. Chaujar, M. Saxena, M. Gupta and R. S. Gupta
2008 Impact of Gate Stack Configuration onto the RF/analog Performance of ISE MOSFET International Conference on Recent Advancements in Microwave Theory and Applications (Microwave-2008), Jaipur, India, November 21-24, 2008 R. Chaujar, M. Saxena, M. Gupta and R. S. Gupta
2008  Development Board-Level Experimentation and Simulation of FPGA based DEBPSK DSSS Modulator: Implementation of 10-Chip Gold Code Sequence Generator Second National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2008) 26-28 September 2008, New Delhi, India R. Chaujar, M. Saxena and R. S. Gupta
2008 Simulation of a Novel ISE MOSFET with Gate Stack Configuration Second National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2008) 26-28 September 2008, New Delhi, India Rishu Chaujar, Manoj Saxena, Mridula Gupta and  R. S. Gupta
 2008 High Temperature Performance of AlGaN/GaN HEMT Second National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2008) 26-28 September 2008, New Delhi, India Parvesh, Sujata Pandey, Subhasis Haldar, Mridula Gupta and R S Gupta
2009 Analytical Drain Current Evaluation Technique for Various Non-Uniformly Doped MOS Device Architectures International Symposium on Microwave and Optical Technology (ISMOT) – 2009, December 16-19, 2009 in Hotel Ashok, New Delhi, India.  Manoj Saxena, Mridula Gupta and R.S. Gupta
Participation in Corporate Life
Summer Internship at Centre for development of telematics (CDOT) at Pusa road, Data communication in optical medium. Worked on C-DOT OMUX-32 
  1.  Curriculum development       
    • Member of the committee for course revision of B.Sc. (H) Electronics and convener for Paper ELHT 401- Numerical Techniques at  Department of Electronics, University of Delhi South Campus, 2012
    • Member of the committee for course revision of B.Sc. (H) Electronics for Paper 3.3- Communications at Department of Electronics, University of Delhi South Campus, 2010-2011.     

       2.    Cultural/ extra curricular activity    
                          
Member, Electronics Club, 2007-09         

       3.    Sports/ community and extension services
                            Member, Women Students Affairs Committee “SASHAKT”, 2008-2009

       4.    Administrative assignment 

  •   Teacher-in-Charge, Department of Electronics, 2012-14
  •   Member, Admission Committee, 2012-14 
  •   Member, Purchase Committee, Department of Electronics, 2012-14
  •   Member, Library Committee, 2012-14
  •   Member, Time Table and Workload Committee, 2012-14
  •   Member, IT Committee, 2008-12  
  •   Member, Finance Committee, 2011-2012
  •   Member, Central Purchase Committee, 2010-11               

                                             

                     
                             

essional Societies Memberships
  • Member IEEE, USA (February 2009) Membership No. 90476328
  • Member IEEE Communication Society (February 2009)
Workshops Conducted
  • Part of Infrastructure Team in National Symposium on recent advances in microwaves and light waves (NSAML’03) University of Delhi South Campus, New Delhi, October 2003.
  • Part of Infrastructure Team in Symposium on recent advances in Telecommunication Systems and Technologies (2004) at University of Delhi South Campus.
  • Member of organizing committee in Asia Pacific Microwave Conference 2004 (APMC ’04) December 15-18 2004.
  • Member of organizing committee in Short course on "Spice Models for Advanced VLSI Circuit Simulation" organized by Department of Electronic Science, University of Delhi South Campus, December 11-12, 2005.
  • Member of organizing committee in Mini-Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed mode Applications-2008, January 5-6, 2008, University of Delhi South Campus, New Delhi, India.
  • Resource Person and member of organizing committee in workshop “Electrawork 2008" on "Data Acqusition software LabVIEW and PCB designing and Fabrication" organized by Department of Electronics, Acharya Narendra Dev College, University of Delhi, Govindpuri, Kalkaji, New Delhi, June 10-20, 2008.
  • Member of organizing committee in workshop “Electrawork 2009" on " Emerging Trends in Electronics" organized by Department of Electronics, Acharya Narendra Dev College, University of Delhi, Govindpuri, Kalkaji, New Delhi, 01-12 June, 2009.     
  • Attended and member of organizing committee in 12th International Symposium on Microwave and Optical Technology (ISMOT-2009) organized by Department of Electronic Science, University of Delhi South Campus, Hotel Ashok, New Delhi, India, 16-19 December, 2009.
Other Academic Contributions
  • Worked as a member of the ILLL (Institute of Life Long Learning, University of Delhi) team involved in writing the e-chapters and preparing the e-exercises for undergraduate students of Applied Physical Sciences.

WORKSHOPS/ CONFERENCES ATTENDED
 

  • Participated in the Jury Process of INSPIRE (INNOVATION IN SCIENEC PURSUIT FOR INSPIRED RESEARCH AWARD National Level Exhibition and Project Competition (NLEPC)- 2013 organised by the Department of Science and Technology during October 08-10, 2013 at Pragati Maidan. New Delhi.
  • Attended “MATLAB & SIMULINK Academic Tour 2013” of Math works at Cluster Innovation Centre on September 23, 2013, University of Delhi.
  • Participated in the “National Workshop on VLSI Designing using Verilog Coding” organized by Bhaskracharya College of Applied Science, University of Delhi, 16-18 July 2013.
  • Participated in the workshop of Foundation Course- Information Technology at Centre for Professional Development in Higher Education, University of Delhi during May 23- 25, 2013.
  • Attended workshop on “Trans-disciplinary Areas of Research & Teaching by Shanti Swaroop Bhatnagar awardee at Deen dayal Updhyaya College, University of Delhi jointly organized by IEEE EDS Delhi Chapter, during February 01-02, 2013.
  • Participated in the Jury Process of INSPIRE (INNOVATION IN SCIENEC PURSUIT FOR INSPIRED RESEARCH AWARD National Level Exhibition and Project Competition (NLEPC)- 2012 organised by the Department of Science and Technology during October 21-23, 2012 at Pragati Maidan. New Delhi.
  • Attended Two Days Joint Science Academies Lecture Workshop On “History, Aspects and Prospects of Electronics in India” during October 12-13, 2012 at : SP Jain Centre Auditorium, University of Delhi South Campus, Benito Juarez Road, Dhaula Kuan, New Delhi, 110021
  • Attended Two Days Mini-Colloquia on "Compact Modelling Techniques for Nanoscale Devices and Circuit Analysis” during March 14-15, 2012 at Arts Faculty Building, University of Delhi South Campus, Benito Juarez Road, New Delhi, 110021
  • Participated in the workshop “Experiments & Research Applications with National Instruments LabVIEW" organized by Bhaskaracharya College of Applied Science (University of Delhi) Sec-2, Phase-I, Dwarka, New Delhi, 2-3 February 2012.
  • Attended National Seminar on Teaching Redefined: Open Access to Education, organized by Acharya Narendra Dev College, University of Delhi, November 1, 2011.
  • Presented a paper entitled  “Analytical Drain Current Evaluation Technique for Various Non-Uniformly Doped MOS Device Architectures” authored by Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta and also member of organizing committee in 12th International Symposium on Microwave and Optical Technology (ISMOT-2009) organized by Department of Electronic Science, University of Delhi South Campus, Hotel Ashok, New Delhi, India, 16-19 December, 2009.
  •  Attended Workshop on “Easy Now-1:A Workshop on Multimedia Content Development”, jointly organized by Acharya Narendra Dev College, University of Delhi and Commonwealth Educational Media Centre for Asia during 20-25th April 2009.
  • Presented paper entitled "Impact of Gate Stack Configuration onto the RF/analog Performance of ISE MOSFET” authored by Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta in International Conference on Recent Advancements in Microwave Theory and Applications (Microwave-2008), Jaipur, India, November 21-24, 2008
  •  Presented paper entitled “Simulation of a Novel ISE MOSFET with Gate Stack Configuration” authored by Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta in Second National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2008), September 26-28, 2008 in New Delhi, India.
  • Presented paper entitled “TCAD Performance Investigation of a Novel MOSFET Architecture of Dual Material Gate Insulated Shallow Extension Silicon On Nothing (DMG ISE  SON) MOSFET for ULSI era” authored by Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta in Asia Pacific Microwave Conference (APMC)-2008, 16-19, December 2008 in Hong Kong Convention and Exhibition Center, Hong Kong, China
  • Presented paper entitled “Analytical Analysis of Sub-Threshold Performance of Sub-100nm Advanced MOSFET Structures-An Iterative Approach” authored by Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta and member of organizing committee Mini-Colloquia on Compact Modeling of Advance MOSFET Structures and Mixed mode Applications-2008, 5-6 January, 2008, University of Delhi South Campus, New Delhi, India.
  • Attended workshop on Linux and Open System Software held at Acharya Narendra Dev College, New Delhi- 6-7 December, 2007.
  • Presented paper entitled  “Dual Material Gate (DMG) SOI-MOSFET with Dielectric Pockets: Innovative Sub-50 nm design for improved switching performance” authored by Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, Indo-Australian Symposium on Multifunctional Nanomaterials, Nanostructures and Applications (MNNA 2007), December 19–21, 2007, New Delhi, India.
  • Presented paper entitled  “Effect of transport property on the performance of insulated shallow extension gate stack (ISEGaS) MOSFET” authored by Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta in Indian microelectronics Society Conference 2007 Theme: Trends in VLSI and Embedded System, Panjab Engineering College, Chandigarh, India, August 17-18, 2007.
  •  Attended Workshop on “Linux and Open System Software”, organized by Open LX Linux held at Acharya Narendra Dev College, University of Delhi during 6-7th December 2007.
  • Attended National Workshop on VLSI Design and Embedded System (NWVDES) held at Birla Institute of Technology and Science, Pilani- 24-26 February 2006.
  • Presented paper entitled “RF Performance Investigation of Gate Stacked Insulated Shallow Extension (ISE) MOSFET and Bulk: A Comparative Study” authored by Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta in National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2006), 24-26 March 2006, New Delhi, India.
  • Presented paper entitled “Lateral Channel Engineered Structure- Insulated Shallow Extension (ISE) MOSFET: DC and RF Performance Investigation” authored by Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta in National Conference on Recent Advancement in Microwave Technique and Applications (Microwave-2006), 6-8 October 2006, Jaipur, India
  • Presented paper entitled “Investigating the role of Stacked Gate Oxide and Hetro-Material Gate on Electrical Characteristics of Insulated Shallow Extension (ISE) MOSFET” authored by Ravneet Kaur, Manoj Saxena and R. S. Gupta in  Thirteenth International Workshop  on Physics of Semiconductor Devices (IWPSD-2005), Vol. 2, pp 1163-1166, 13-17 December 2005,New Delhi India.

Research  Experience (Besides teaching):

  •  Reviewer IEEE Transaction on Electron Devices
  • Reviewer of International Conference - Asia Pacific Microwave Conference (APMC)-2008 to be held from 16-19, December 2008 in Hong Kong Convention and Exhibition Center, Hong Kong, China.